Sitota Ezra Mersha
Portrait of Sitota Ezra Mersha

Sitota Ezra Mersha

Ph.D. Student, Computer Science & Engineering
University of Michigan

I am a Ph.D. student at the University of Michigan, advised by Prof. Ronald G. Dreslinski Jr. I work on computer architecture, with a focus on memory systems and hardware–software co-design for privacy: making oblivious memory and oblivious retrieval fast enough to use in practice. I am also interested in using machine learning to speed up hardware design and simulation.

Before Michigan, I earned a B.S. in Software Engineering from Addis Ababa Institute of Technology and worked as a software engineer at CIMMYT and ILRI.

Publications

ForeSight: Prescient Prefetching in Disaggregated Memory

Under review

Nada Abdalgawad, Sitota Mersha, Nicholas Wendt, Valeria Bertacco

A hardware–software co-design that turns the static memory access patterns of data-oblivious programs into a page prefetch schedule for disaggregated memory. I designed and implemented the ForeSight prefetch accelerator, which delivers a 4–54× speedup over LRU page replacement with under 0.1% area overhead.

Research

Starling

Fall 2026 – present

Sitota Mersha, Haoran Jin, Amrita Roy Chowdhury, Ronald Dreslinski, Nathaniel Bleier

Hardware–software co-design to make oblivious retrieval practical for retrieval-augmented generation (RAG) over sensitive data, at interactive latency and scale.

Learned Microarchitectural Warm-Up for Fast Design Space Exploration

Summer 2026 – present

Ivris Raymond, Sitota Mersha, Ronald Dreslinski

Learned models of microarchitectural state as a faster alternative to repeated simulator warm-up, so design space exploration can evaluate far more CPU designs at gem5 accuracy.

ML for Maintaining Obsolete Digital Systems

2025 – 2026

Ivris Raymond, Sitota Mersha, Valeria Bertacco

An LLM-agent system that engineers drop-in RTL replacements for failing, obsolete components in high-reliability systems. I built the testing infrastructure and RTL design library and benchmarked LLMs on RTL generation; structured prompts improved RISC-V pipeline correctness by 44–50%. Presented as From Prompt to Processor at the DAC 2025 Young Fellows poster session.

Poster

Selected Projects

Improving APT-GET via Distance Correction, Locality Control, and Intra-Loop Prefetching

EECS 583

Extended the APT-GET LLVM software prefetcher with capacity-aware distance tuning, per-load distances and cache locality, and intra-loop prefetching, reaching up to 1.33× speedup over APT-GET on graph workloads.

Report

Batching and Request Aggregation for LLM Inference on CPUs

CSE 585

Implemented request aggregation and batching in llama.cpp, reducing response time by 20%.

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Experience

Education

Awards & Honors

Service & Mentoring